1. Field of the Invention
The present invention relates to trench gate MOS FET structures having a diffusion layer, a gate oxide film, a gate and an isolation.
2. Description of the Prior Art
A conventional MOS FET has a structure such as that shown in FIG. 7. This is a conventional MOS FET fabricated by forming a field SiO.sub.2 film 702, a gate SiO.sub.2 film 703 and a gate electrode 704, a source impurity diffusion layer (hereinunder referred to as "source diffusion layer") 705, and a drain impurity diffusion layer 706 (hereinunder referred to as "drain diffusion layer") on the Si substrate 701, further forming a low concentration diffusion layer 707 which is in contact with at least the drain diffusion layer 706, and extending lead-out electrodes from the source diffusion layer 705, the-gate electrode 704 and the drain diffusion layer 706 to provide a source S, a gate G and a drain D, respectively.
In contrast, a trench gate MOS FET such as that shown in FIG. 8 has recently been proposed. This MOS FET is generally fabricated by providing a field SiO.sub.2 film 802 and a trench portion on an Si substrate 801, forming a gate SiO.sub.2 film 803, a gate electrode 804, a source diffusion layer 805 and a drain diffusion layer 806 in the trench portion, and extending lead-out electrodes from the source diffusion layer 805, the gate electrode 804 and the drain diffusion layer 806 so as to form a source S, a gate G and a drain D, respectively.
Another proposal has been made by Yutaka Hayashi in "Ambition for High Integration in the Order of Giga Bit" (Science and Technique in Japan, 27, 242, pp. 46 to 47 (1986)). This MOS FET is called an X-MOS, and has a structure such as that shown in FIG. 9. More specifically, an X-MOS is fabricated by laminating, in the order stated, an interlayer dielectric film 913, a first gate electrode 904, a second gate SiO.sub.2 film 903 and an Si substrate 901 consisting of a semiconductor Si film on the surface of a substrate 912 of a glass material or the like; then providing a source diffusion layer 905 and a drain diffusion layer 906 on the Si substrate 901; and further providing a second gate SiO.sub.2 film 903' and a second gate electrode 904'.
Furthermore, the isolation of a device by trench isolation, the formation of a trench gate, etc., have conventionally been proposed independently of each other for a MOS FET.
In the prior art, however, it has never been suggested to form a low concentration diffusion layer which is adjacent to a drain diffusion layer with a view to preventing the generation of hot electrons in an MOS FET having what is called a trench gate structure. This is probably because it is considered that since it is possible to keep the channel length of a trench long by making the depth of the trench sufficiently large in a trench gate structure, the generation of hot electrons can substantially be reduced with even a small gate length. Even in such a trench gate MOS FET, however, a great effort has been made to make the trench depth as small as possible. If the trench depth is made too small, however, hot electrons are produced due to the enhancement of the field strength in the vicinity of the drain, which leads to fluctuations in threshold value, thereby disadvantageously reducing long term reliability.
In a conventional trench gate MOS FET as shown in FIG. 8, the gate SiO.sub.2 film 803 and the gate electrode 804 are formed in the trench portion provided on the surface of the Si substrate 801, and the thickness of the portion of oxide film 803 which overlaps gate electrode 804 is generally the same on the surface of the source diffusion layer 805 and the drain diffusion layer 806 as the thickness of the other portion of film 803. This structure is disadvantageous in that the electric capacitance at the overlapping portion of the gate electrode overlaps and the diffusion layer increases, thereby lowering the switching speed of the trench gate MOS FET device.
In the prior art device shown in FIG. 9, it is necessary to adopt a multi-layer structure and it is difficult to form a semiconductor film without producing a crystal defect which may result in an increase in the leakage current in the device characteristics.
Furthermore, in a conventional MOS FET having a trench gate structure, although there is no particular problem in the structure in the lengthwise direction of the gate, the gate width does not have a defined, or reproducible, value due to an indefinite relationship with the isolation portion.